Path Selection Based Acceleration of Conditionals in CGRAs

Description

Accelerators are now widely accepted as an inseparable part of computing fabric. Although some accelerators have been shown to improve performance, they are not programmable and incur a high design cost. Graphics Processing Units (GPUs) are programmable, but are only able to accelerate parallel loops. Coarse Grain Reconfigurable Arrays (CGRAs) are promising accelerators capable of achieving high performance at low power consumption. They are programmable and able to work with complex logic loops such as if-then-else statements. Standard techniques accelerate if-then-else statements by fetching and executing operations from both paths within the loop and committing a single path run time. This results in large efficiency losses through poor mapping and lower acceleration. Thus, there is a pressing need for a method of implementing CGRAs to accelerate computation of complex logic loops without sacrificing performance.

Researchers at Arizona State University have invented a method of efficiently utilizing CGRAs. Loops are accelerated by fetching and executing only the instructions by the path taken by a branch at run time. The branch condition is executed as early in the process as possible, and then immediately communicates its results to the CGRA, which fetches instructions from the correct path. This results in nearly 35% performance improvements and over 50% lower energy consumption.

Potential Applications

  • Semiconductors
  • Personalized electronics
  • High-performance computing
  • supercomputers

Benefits and Advantages

  • Efficiency – only the necessary instructions from the path taken by the branch at run time are fetched and issued to the CGRA.
  • Energy Consumption – Nearly 50% less energy is needed to perform loop accelerations.
  • Speed – ability to accelerate complex logic loops means overall improved computing speed.

For more information about the inventor(s) and their research, please see

Dr. Aviral Shrivastava's directory webpage

For more information about related technologies, please see

M15-048P: GCCFG (Global Call Control Flow Graph): A Data Structure for Inter-procedural Optimizations

Case ID:
M15-100P
Published:
12-17-2015
Last Updated:
05-10-2018

Patent Information

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