Researchers at ASU have developed a low cost reliability modeling approach that accurately predicts CMOS part aging. The technology accurately predicts part aging caused by bias, temperature, and radiation stress over time. The technology is also readily implemented in generic circuit simulators. The approach models the effects of oxide and interfacial defects on the operation of advanced CMOS transistors and integrated circuits.
- Power Electronics
Benefits and Advantages
- Uses Defects Densities for Simulation– Facilitates accurate simulations of reliability treats not simply compact model parameters such as threshold voltage.
- Implemented as a library cell – Can be inserted between a gate voltage stimulus and gate terminal.
- Compatibility – Compatible with most compact modeling approaches, and will not require alterations to specific parameters of compact models.
For more information about the inventor(s) and their research, please see
Dr. Hugh Barnaby's directory webpage