Physics-based reliabilty model for large-scale CMOS circuit design

Description

Designers of commercial integrated circuits in advanced Complementary Metal– Oxide–Semiconductor (CMOS) technologies are increasingly faced with customer demands for highly reliable parts. This is particularly true for developers of strategic defense, medical, space-based, and other applications where long term survivability of circuits is critical. Due to the increasing costs of advanced CMOS processes, the high reliability electronics industry is now utilizing commercial foundries for part fabrication. This creates the need for a new low cost modeling approach that can support the design of reliable circuits before fabrication.

Researchers at ASU have developed a low cost reliability modeling approach that accurately predicts CMOS part aging. The technology accurately predicts part aging caused by bias, temperature, and radiation stress over time. The technology is also readily implemented in generic circuit simulators. The approach models the effects of oxide and interfacial defects on the operation of advanced CMOS transistors and integrated circuits.

Potential Applications

  • Semiconductors
  • Defense
  • Space
  • Power Electronics
  • Medical

Benefits and Advantages

  • Uses Defects Densities for Simulation– Facilitates accurate simulations of reliability treats not simply compact model parameters such as threshold voltage.
  • Implemented as a library cell – Can be inserted between a gate voltage stimulus and gate terminal.
  • Compatibility – Compatible with most compact modeling approaches, and will not require alterations to specific parameters of compact models.

For more information about the inventor(s) and their research, please see
Dr. Hugh Barnaby's directory webpage

Case ID:
M13-036P
Published:
10-09-2013
Last Updated:
05-16-2018

Patent Information

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