Resistive RAM Design with Embedded XNOR Computing

Description

Background

Neuromorphic computing, or the concept of designing systems that mimic the adaptability and learning exhibited by biological neural processes, is the future of computing design.  This type of computing is ideal for use in the Internet of Things (IoT) movement, which refers to the embedding of internet computing devices into everyday objects.  However, the state-of-the-art deep learning algorithms used in neuromorphic computing are difficult to integrate into IoT platforms because of their excessive power use and memory needs.  Therefore, it is necessary to develop a new design that enables neuromorphic computing in IoT contexts in order to further advance the abilities and applications of IoT platforms.

Invention Description

Researchers at Arizona State University have developed a new RRAM bitcell and array design that is able to map in-memory XNOR computing functionality, enabling it to perform in-memory computing in RRAM devices.  RRAM refers to resistive random access memory, and it is a type of nonvolatile computer memory.  XNOR computing is a type of logic-based computing consisting of a logic gate that returns different outputs depending on the nature of the inputs. 

This novel integration of computing technology enables neuromorphic computing capability at a lower power consumption and with a minimized footprint.  Efficiently mapping neural networks creates this ability, using RRAM arrays embedded with XNOR computing to enable in-memory computing.  This design thus enables integration of deep neural networks and IoT platforms.

Potential Applications

•       Non-volatile memory devices

•       Computing

•       Neuromorphic computing

Benefits and Advantages

•       Innovative: Performs XNOR in-memory computing even when wordline is zero

•       Efficient: Lower power and area consumption in function when used in IoT platforms

•       Versatile: Useful in any context involving non-volatile memory

Case ID:
M17-203P
Published:
11-02-2018
Last Updated:
12-05-2018

Inventor(s):

Jae-Sun Seo Shimeng Yu

Patent Information

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