Researchers at Arizona State University have developed a fully automated circuit design and CAD methodology to implement single event effect (SEE) hardened application specific integrated circuits (ASIC) using triple mode redundancy (TMR) synthesis and automated place and route that is fully self-correcting and guarantees effective critical node spacing. The TMR circuits have been experimentally proven in both heavy ion and proton testing on both the low standby power and standard versions of trusted foundry CMOS technology. This technology allows standard non-redundant register transfer language input to synthesize and fully automate placement and routing of circuits, with virtually no timing penalty when compared to unhardened circuitry. The layout of the circuits ensures that critical nodes are suitably placed so as to make the nodes radiation hardened by design.
- Space Vehicles
- High Altitude Flight
- Devices Used Near Nuclear Accidents or Nuclear Warfare
- Dependable - Produces circuits that are radiation hardened
- Easy Application - Simple to use automated place and route of circuitry
- High Speed - Virtually no timing penalty over unhardened circuits